This invention relates to analog-to-digital (A-to-D) converters and, more particularly, to such converters which provide trade-offs between the number of comparators and operating speed.
Analog-to-digital converters (ADC) are widely used for converting analog signal voltages into a plurality of coded binary (two-level) signals, ordinarily known as digital signals. The history of such converters includes requirements for progressively higher operating speeds, in order to accommodate analog signals having progressively higher frequencies. High operating speeds are provided by the well-known flash converter. The flash converter includes N-1 comparators, where N is the number of distinct levels or states represented by the binary number, for producing N-1 unencoded binary signals, which are encoded by an encoding logic circuit to produce the desired digital signal. Such flash converters can make a conversion in one clock cycle, but tend to require relatively high power because of the large number of comparators required, which is one less than the number of possible states of the digital signal (255 comparators for conversion to an 8-bit digital signal). A 12-bit flash converter would require 4095 comparators. Practical limitations make converters for more than eight bits unwieldy at the present state of the art.
The number of comparators is reduced in the subranging or half-flash converter. An 8-bit half-flash converter uses 15 comparators (four bits) to produce a first intermediate digital signal. The first 4-bit intermediate signal represents the four most significant bits (MSB) of the desired digital output signal. The first intermediate signal is then converted back to an analog form for subtraction from the input signal to produce a difference signal. The difference signal is amplified to drive a second 4-bit flash converter which produces the four least significant bits of the output digital signal. The overall conversion operation requires two clock cycles. The half-flash converter has an accuracy which depends upon the accuracy of the analog substractors and of the amplifiers required to amplify the difference signal. Thus, the half-flash converter has fewer comparators than the full flash converter, but requires accurate analog subtractors and amplifiers in order to provide accurate conversion, and, furthermore, requires a longer time for conversion.
The successive approximation type of converter resolves one bit during each clock cycle, starting with the most significant bit. This type of converter requires one clock cycles to resolve eight bits.
An analog-to-digital converter is desired in which fewer comparators are required than for a full flash converter, which does not require accurate analog subtractors and amplifiers, and which is faster than the successive approximation converter.